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General Description
ision(R)
Applications
TM
Advanced Information Preliminary Datasheet
OV5620 Color CMOS QSXGA (5.17 MPixel) CAMERACHIPTM with OmniPixel2TM Technology
The OV5620 (color) CAMERACHIP is a high performance 5.17 mega-pixel image sensor for digital still image and video camera products. This device incorporates a 2592 x 1944 image array and an on-chip 10-bit A/D converter capable of operating at up to 7.5 frames per second (fps) in full resolution. The OV5620 can also output 864 x 600 resolution at 60 fps enabling enhanced video viewing on TV. Proprietary sensor technology utilizes advanced algorithms to cancel Fixed Pattern Noise (FPN), eliminate smearing, and drastically reduce blooming, dark current and lens shading. The control registers allow for flexible control of timing, polarity, and CAMERACHIP operation, which, in turn, allows the engineer a great deal of freedom in product design.
* * * *
Digital still cameras Digital video cameras PC camera/dual mode Video conference equipment
Key Specifications
Array Size Analog Power Supply Digital I/O Power Active Standby Requirements Electronics Exposure Shutter Output Format Lens Size Lens Chief Ray Angle Input Clock Maximum System Clock Maximum Data Rate Full 1.3Mpixel Max Image D1MD Transfer Rate VGA QVGA Sensitivity S/N Ratio Dynamic Range Scan Mode Pixel Size Dark Current Fixed Pattern Noise Image Area Package Dimensions 2592 x 1944 2.6 ~ 3.0V 1.3V + 5% 1.7 ~ 3.3V TBD 250 A 1 TLINE to 1/F where F = frame rate Electronic rolling shutter, snapshot 10-bit digital RGB Raw data 1/2.5" 12.5 6 - 27 MHz 48 MHz 48 MHz 7.5 fps 30 fps 60 fps 60 fps 120 fps TBD TBD TBD Progressive 2.2 m x 2.2 m TBD TBD 5.808 mm x 4.294 mm 14.22 mm x 14.22 mm
Pb
Features
* * * * * * * * * * * * * * * * * *
Note: The OV5620 is available in a lead-free package.
Optical black level calibration Video or snapshot operations Programmable/Auto Exposure and Gain Control Programmable/Auto White Balance Control Horizontal and vertical sub-sampling for high frame rate with excellent image quality High frame rate output mode Programmable image windowing Variable frame rate control On-chip Luminance Average Counter VarioPixel(R) (binning) 1:2, 1:3, 1:4 Subsampling (skip) 1:2, 1:3, 1:4, 1:8 Flash control output (strobe pin) 50/60 Hz light auto detection Image vertical flip / horizontal mirror Defect pixel correction Internal/External frame synchronization Serial bus interface Power-on reset and power-down modes
Figure 1 OV5620 Pin Diagram (Top View)
DATA_N DATA_P DOGND XVCLK CLK_N CLK_P DGND EGND AVDD PVDD EVDD NC 18 NC 17 NC 16 Y3 15 Y2 14 Y1 13 Y0 12 EXP_STB 11 RESET_B 10 FREX 9 8 7 43 44 45 46 47 48 VSYNC HREF SVDD AGND SDA SCL 1 DOVDD 2 STROBE 3 RVDD 4 VREF1 5 VREF2 6 NC PWDN NC NC
30 29 28 27 26 25 24 23 22 21 20 19 NC 31 NC 32 DVDD 33 Y4 34 Y5 35 Y6 36 Y7 37 Y8 38
OV5620
Ordering Information
Product OV05620-C03A (Color) Package CLCC-48
Y9 39 PCLK 40 NC 41 NC 42
5620CLCC_DS_001
(c) 2006 OmniVision Technologies, Inc.
Version 1.1, May 9, 2006
VarioPixel, OmniVision, and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniPixel2 and CameraChip are trademarks of OmniVision Technologies, Inc. These specifications are subject to change without notice.
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM Functional Description
Figure 2 shows the functional block diagram of the OV5620 image sensor. The OV5620 includes: * Image Sensor Array (2592+16) x (1944+4) resolution) * Analog Amplifier * Gain Control * Balance Control * * * * * * *
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ision
10-Bit A/D Converter Test Pattern Generator Digital Signal Processor (DSP) Snapshot (Frame Exposure) Mode Timing Frame Rate Adjust SCCB Interface Channel Average Calculator
Figure 2 Functional Block Diagram
Buffer
Digital Video Port (DVP)
Y[9:0] PCLK HREF VSYNC
Test Pattern Generator DSP AMP 10-Bit A/D 50/60 Hz Auto Detect Image Array Gain Control Balance Control Control Register Bank
(White/black pixel correction, etc.)
Compact Camera Port (CCP)
Column Sense Amps
CP CN DP DN
Frequency Doubler
Row Select
Timing Generator and Control Logic
SCCB Slave Interface
XVCLK
RESET_B
PWDN
FREX
EXP_STB
SCL
SDA
5620CLCC_DS_002
Image Sensor Array
The OV5620 sensor is a 1/2.5-inch CMOS imaging device. The sensor contains 5,174,400 pixels. Figure 3 shows the color filter layout. The color filters are in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion. Of the 5,174,400 pixels, 5,080,384 are active. The other pixels are used for black level calibration and interpolation. The sensor array design is based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel read-out scheme.
Figure 3 Sensor Array Region Color Filter Layout
Column R o0BG w1G R
0 2 3 4 5G 6 B R G R G G B G B R G R G G B G B R G R G G B G B R G R G G B G B R G R G G B G B R G R G 1944 Active Lines 1951 1952 G B R G G B R G G B R G G B R G G B R G G B R G 8 Dummy Lines 1959 G R G R G R G R G R G R
5620CLCC_DS_003
2634
2635
2636
2637
2638 B G B
B G B
G R G
B G B
G R G
B G B
G R G
B G B
G R G
G R G
2639
1
2
3
4
5
Dummy Dummy Dummy Optical Black Dummy Dummy Dummy
B
G
7G 8 B
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Functional Description
Analog Amplifier
When the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier.
Digital Signal Processor (DSP)
* * White/black pixel correction Lens shading correction
Windowing Gain Control
The amplifier gain can either be programmed by the user or controlled by the internal automatic gain control circuit (AGC). The gain adjustment range is 0-24 dB. The OV5620 allows the user to define window size or region of interest (ROI), as required by the application. Window size setting (in pixels) ranges from 2 x 4 to 2592 x 1944 (QSXGA) or 2 x 2 to 1280 x 960 (1.3 Mpixel) and 640 x 480 (VGA), and can be anywhere inside the 2592 x 1944 boundary. The windowing control merely alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical ROI.
Balance Control
Channel balance can be done manually by the user or by the internal automatic white balance (AWB) controller.
Figure 4 Windowing
Column Start Column End
10-Bit A/D Converter
The balanced signal is then digitized by the on-chip 10-bit ADC. It can operate at up to 27 MHz and is fully synchronous to the pixel clock. The actual conversion rate is determined by the frame rate.
HREF
R Column o w
Row Start HREF Display Window
Test Pattern Generator
The Test Pattern Generator features the following: * 8-bar color bar pattern * Fade-to-gray color bar pattern * Shift "1" in output pin
Row End
Sensor Array Boundary
5620CCLCC_DS_004
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
VarioPixel (Binning) 1:2, 1:3, 1:4
Figure 5 Horizontal/Vertical 1:2 Average (Binning) Figure 9 Vertical 1:4 Average (Binning)
B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R
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ision
B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr
Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R
B Gr B Gr B Gr B Gr B Gr B Gr B Gr B Gr
Gb R Gb R Gb R Gb R Gb R Gb R Gb R Gb R
5620CLCC_DS_009
B
Gb B
Gb B Gr Gb R
5620CLCC_DS_005
B Gr B
Gr R B
Gr R Gb
Gr B Gr B Gr
Gb B
Gr R
Gr R
B Gr B Gr
Figure 6 Horizontal 1:3 Average (Binning)
B Gr
B Gr
Gb R
B Gr
Gb R
B Gr
Gb R
B Gr
Gb R
Flash Control Output (Strobe Pin)
The OV5620 has a Strobe mode that allows it to work with an external flash and LED.
5620CLCC_DS_006
Figure 7 Vertical 1:3 Average (Binning)
B Gr B Gr B Gr B Gr B Gr B Gr Gb R Gb R Gb R Gb R Gb R Gb R
5620CLCC_DS_007
Snapshot (Frame Exposure) Mode Timing
The OV5620 supports snapshot (frame exposure) mode. Typically, the snapshot mode must work with the aid of an external shutter. The frame exposure pin, FREX (pin 10), is the snapshot mode enable pin and the EXP_STB pin (pin 12) serves as the sensor's exposure start trigger. When the external master device asserts the FREX pin high, the sensor array is quickly pre-charged and stays in reset mode until the EXP_STB pin is pulled low (sensor exposure time can be defined as the period between EXP_STB low to shutter close). After the FREX pin is pulled low, the video data stream is then clocked to the output port in a line-by-line manner. After completing one frame of data output, the OV5620 will output continuous live video data unless in single frame transfer mode. Figure 17 shows detailed timing of the Frame Exposure mode and Table 10 shows the timing specifications for this mode. When the OV5620 is working in snapshot mode, every line is sampled at different times causing different dark current levels line-by-line. To eliminate the dark current difference, the OV5620 provides line optical black pixel output. The difference in dark current can be calibrated line-by-line.
B Gr B Gr
Gb R Gb R
Figure 8 Horizontal 1:4 Average (Binning)
B Gr
Gb B R Gr
Gb B R Gr
Gb B R Gr
Gb B R Gr
Gb B R Gr
Gb B R Gr
Gb B R Gr
Gb R
B Gr
Gb R
5620CLCC_DS_008
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ision
Functional Description
Frame Rate Adjust
The OV5620 offers four methods for frame rate adjustment: * Clock prescaler: (see "CLKRC" on page 17) By changing the system clock divide ratio, the frame rate and pixel rate will change together. This method can be used for dividing the frame/pixel rate by: 1/2, 1/3, 1/4 ... 1/64 of the PLL output clock. * Horizontal blanking: (see "REG2A" on page 20 and see "EXHCL" on page 20) By changing the horizontal blank timing in each line after active pixel output, the frame rate can be changed while leaving the pixel rate as is. * Vertical blanking: By adding dummy line periods to the vertical sync period (see "ADDVSL" on page 20 and "ADDVSH" on page 20) or after the active lines (see "DMLNL" on page 21 and "DMLNH" on page 21), the frame rate can be altered while the pixel rate remains the same. * PLL control: Supports more flexible clock control
Figure 10 Slave Mode Connection
Y[9:0] RESET_B PWDN XVCLK MHSYNC MVSYNC MCLK
OV5620
Master Device
5620CLCC_DS_010
Figure 11 Slave Mode Timing
T frame VSYNC T VS HSYNC MCLK Tclk
5620CLCC_DS_011
T line
T HS
SCCB Interface
The OV5620 provides an on-chip SCCB serial control port that allows access to all internal registers, for complete control and monitoring of OV5620 operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port.
NOTE: 1) THS > 6 Tclk, Tvs > Tline 2) Tline = 3252 x Tclk (QSXGA); Tline = 1640 x Tclk (1.3 Mpixel) 3) Tframe = 1968 x Tline (QSXGA); Tframe = 976 x Tline (1.3 Mpixel)
Channel Average Calculator
The OV5620 provides average output level data for frame-averaged luminance level. Access to the data is provided via the SCCB interface.
Slave Operation Mode
The OV5620 can be programmed to operate in slave mode (default is master mode). When used as a slave device, the OV5620 re-uses input pins, RESET_B and PWDN, for use as horizontal and vertical synchronization input triggers supplied by a master device. The master device must provide the following signals: 1. 2. 3. System clock MCLK to XVCLK pin Horizontal sync MHSYNC to RESET_B pin Vertical frame sync MVSYNC to PWDN pin
Reset_B
The OV5620 includes a RESET_B pin (pin 11) that forces a complete hardware reset when it is pulled low (ground). The OV5620 clears all registers and resets them to their default values when a hardware reset occurs. A reset can also be initiated through the SCCB interface.
Power Down Mode
Two methods are available to place the OV5620 into power-down mode. * Hardware power-down may be selected by pulling the PWDN pin (pin 9) high (DOVDD). When this occurs, the OV5620 internal device clock is halted and all internal counters are reset. The current draw is less than 250 A in this standby mode. * Software power-down through the SCCB interface suspends internal circuit activity but does not halt the device clock. The current requirements drop to less than 1 mA in this mode. All register content is maintained in standby mode. Proprietary to OmniVision Technologies, Inc. 5
See Figure 10 for slave mode connections and Figure 11 for detailed timing considerations.
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Digital Video Port MSB/LSB Swap
The OV5620 has a 10-bit digital video port. The MSB and LSB can be swapped with the control registers. Figure 12 shows some examples of connections with external devices.
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ision
Also, PCLK output can be programmed using register COM10[5] to be gated by the active video period defined by the HREF signal. See Figure 13 for details.
Figure 13 PCLK Output Only at Valid Pixels
PCLK
PCLK active edge negative
HREF PCLK
PCLK active edge positive
Figure 12 Connection Examples
MSB Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 LSB Y0 OV5620 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 External Device LSB Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 MSB Y0 OV5620 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 External Device
VSYNC
5620CLCC_DS_013
The specifications shown in Table 8 apply for DVDD = +1.3 V, DOVDD = +3.3 V, TA = 25C, sensor working at 10 fps, external loading = 30 pF.
Pixel Output Pattern
Table 1 shows the output data order from the OV5620. The data output sequence following the first HREF and after VSYNC is: B0,0 G0,1 B0,2 G0,3... B0,2590 G0,2591. After the second HREF the output is G1,0 R1,1 G1,2 R1,3... G1,2590 R1,2591..., etc.
Default 10-bit Connection
Swap 10-bit Connection
MSB Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 LSB Y0 OV5620
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
LSB Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 MSB Y0 OV5620
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 External Device
Table 1
R/C 0 1 2 3 . . 0 B0,0 G1,0 B2,0 G3,0 1
Data Pattern
2 B0,2 G1,2 B2,2 G3,2 3 G0,3 R1,3 G2,3 R3,3 ... ... ... ... ... . . B1942,2590 G1942,2591 G1943,2590 R1943,2591 2590 B0,2590 G1,2590 B2,2590 G3,2590 2591 G0,2591 R1,2591 G2,2591 R3,2591
G0,1 R1,1 G2 R3,1
External Device
Default 8-bit Connection
Swap 8-bit Connection
5620CLCC_DS_012
1942 B1942,0 G1942,1 B1942,2 G1942,3
Line/Pixel Timing
The OV5620 digital video port can be programmed to work in either master or slave mode. In both master and slave modes, pixel data output is synchronous with PCLK (or MCLK if port is a slave), HREF, and VSYNC. The default PCLK edge for valid data is the negative edge but may be programmed using register COM10[4] for the positive edge. Basic line/pixel output timing and pixel timing specifications are shown in Figure 15 and Table 8.
1943 G1943,0 R1943,1 G1943,2 R1943,3
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ision
Pin Description
Pin Description
Table 2
Pin Number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Pin Description
Name DOVDD STROBE RVDD VREF1 VREF2 NC NC NC PWDN FREX RESET_B EXP_STB Y0 Y1 Y2 Y3 NC NC NC EVDD CLK_P CLK_N DATA_P DATA_N EGND PVDD XVCLK DOGND AVDD DGND NC Pin Type Power Output Power Analog Analog - - - Input (0) Input (0) Input (1) Input (0) Output Output Output Output - - - Power Output Output Output Output Power Power Input Power Power Power - Function/Description Power for I/O circuit (1.7V to 3.3V) LED control output Regulator power (2.8V) Internal reference - connect to ground using a 0.1 F capacitor Internal reference - connect to ground using a 0.1 F capacitor No connection No connection No connection Power down control, active high (hardware standby) Frame exposure control 1 Hardware reset, active low Frame exposure control 2 Bit[0] of video output port Bit[1] of video output port Bit[2] of video output port Bit[3] of video output port No connection No connection No connection CCP2 power (2.8V) CCP2 positive clock output CCP2 negative clock output CCP2 interface positive data output CCP2 interface negative data output CCP2 ground PLL power (2.8V) System clock input Ground for I/O circuit Analog power (2.8V) Digital ground No connection
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Table 2
Pin Number 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NC DVDD Y4 Y5 Y6 Y7 Y8 Y9 PCLK NC NC VSYNC HREF SCL SDA SVDD AGND
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ision
Pin Description (Continued)
Name Pin Type - Power Output Output Output Output Output Output Output - - Output Output Input I/O Power Power No connection Internal reference - connect to ground using a 0.1 F capacitor or digital power (1.3V) Bit[4] of video output port Bit[5] of video output port Bit[6] of video output port Bit[7] of video output port Bit[8] of video output port Bit[9] of video output port Pixel clock output No connection No connection Vertical synchronization output Horizontal reference (data valid) output I2C clock I2C data Analog power (2.8V) Analog ground Function/Description
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ision
Electrical Characteristics
Electrical Characteristics
Table 3 Operating Conditions
Parameter Operating temperature Storage temperaturea
a.
Min -20 -40
Max +70 +125
Unit C C
Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operation of the sensor at these and any other condition above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for any extended period may affect reliability.
Table 4
Symbol Supply VDD1 VDD2 VDD3 IDD-VDD1 IDD-VDD2 IDD-VDD3
DC Characteristics (-20C < TA < 70C, Voltages referenced to GND)
Parameter Min Typ Max Unit
Supply voltage (RVDD, EVDD, PVDD, AVDD, SVDD) Supply voltage (DOVDD) Supply voltage (DVDD) Supply current (QSXGA at 7.5 fps) Supply current (QSXGA at 7.5 fps) Supply current (QSXGA at 7.5 fps)
2.6 1.7 1.24
2.8 2.8 1.3 TBD TBD TBD
3.0 3.3 1.37
V V V mA mA mA
Digital Inputs VIL VIH CIN Input voltage LOW Input voltage HIGH Input capacitor 0.7 x VDD2 10 0.3 x VDD2 V V pF
Digital Outputs VOH VOL Output voltage HIGH Output voltage LOW 0.9 x VDD2 0.1 x VDD2 V V
SCCB Inputs VIL VIH SCL and SDA SCL and SDA 0.7 x VDD2 0.3 x VDD2 V V
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ision
Table 5
Symbol
AC Characteristics (TA = 25C)
Parameter Min Typ Max Unit
ADC Parameters B DLE ILE Analog bandwidth DC differential linearity error DC integral linearity error Settling time for hardware reset Settling time for software reset Settling time for 1.3 Mpixel/QSXGA mode change Settling time for register setting 24 0.5 1 <1 <1 <1 <300 27 MHz LSB LSB ms ms ms ms
Table 6
Symbol
Timing Characteristics
Parameter Min Typ Max Unit
Oscillator and Clock Input fOSC tr, tf Frequency (XVCLK) Clock input rise/fall time Clock input duty cycle 45 50 6 24 27 2 55 MHz ns %
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Timing Specifications
Timing Specifications
Figure 14 Serial Bus Timing Diagram
tF t LOW SCL t SU:STA SDA IN t BUF tAA SDA OUT
5620CLCC_DS_014
t HIGH
tR
t HD:STA
t HD:DAT
t SU:DAT
tSU:STO
t DH
Table 7
Symbol fSCL tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH
Serial Bus Timing Specifications
Parameter Clock Frequency Clock Low Period Clock High Period SCL low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time Serial Bus Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 Min Typ Max 400 Unit KHz s ns ns s ns ns s ns ns ns ns
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Figure 15 QSXGA, 1.3 Mpixel, VGA and HF Mode Line/Pixel Output Timing
tp PCLK or MCLK t pr t pf
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ision
t dphr HREF
t dphf
t su Y[9:0] P 1279/2591 Invalid Data P0 t dpd
t hd P1 P2 P 1078/2590 P 1279/2591
5620CLCC_DS_015
Table 8
Symbol tp tpr tpf tdphr tdphf tdpd tsu thd
Pixel Timing Specification
Parameter PCLK period PCLK rising time PCLK falling time PCLK negative edge to HREF rising edge PCLK negative edge to HREF negative edge PCLK negative edge to data output delay Data bus setup time Data bus hold time 0 0 0 15 8 Min Typ 20.83 4 1 5 5 5 Max Unit ns ns ns ns ns ns ns ns
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ision
Timing Specifications
Figure 16 Frame Timing
TFRAME VSYNC 4 x TLINE HB1 HREF VSYNC NOTES: 1. 2. 3. 4. TFRAME = TVALID + VBLANK HBLANK = HB1 + HB2 TLINE = H + HBLANK VBLANK = VB1 + VB2 + VSYNC
5620CLCC_DS_016
TVALID
HB2
HB1
HB2
VB2
VB1 H HBLANK
Table 9
Format 5 Mpixel 1.3 Mpixel D1MD QFMDc HFd
a. b. c. d.
Control Parameters for Standard Resolution Output
H_Size (pixels) 2592 1280 864 1280 1280 V_Size (pixels) 1944 960 600 480 240 H_Bin 1:1 1:2 1:3 1:2 1:2 V_Bin 1:1 1:2 1:3 1:4 1:8 VB2 0 0 0 0 0 VSYNC 4 4 4 4 4 VB1 20 13 13 13 13 HB1 192 192 192 192 192 HB2a 468 168 244 140 88 HBLANK( pixels) 660 360 436 332 280 VBLANK (TLINES) 24 17 17 17 17 Frame Rateb (fps) 7.5 30 60 60 120
HB2 = HBLANK - HB1 Frame Rate listed is based on 48MHz internal system clock VGA (640x480) is derived from QFMD with 2:1 times skip/average in horizontal direction to get 60fps based on 24MHz PCLK (48MHz/2) QVGA (320x240) is derived from HF with 4:1 times skip/average in horizontal direction to get at 120fps based on 12MHz PCLK (48MHz/4)
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Figure 17 Snapshot Mode Timing with EXP_STB Asserted
Shutter Open Shutter FREX t des EXP_STB t pre Sensor Timing VSYNC t dvh HREF Y[9:0] Row X Row 0 Row 1 Row 1943
Sensor Precharge
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ision
tdef
Turn ON Flash Exposure Time
t dfvr
t dfvf
t dvsc
No following live video frame if set to transfer single frame
5620CLCC_DS_017
Table 10
Snapshot Timing Specifications
Symbol Min Typ 3252 (QSXGA) 8 8 2 17 (QSXGA) 0 20 230 (QSXGA) 9 Max Unit tp tp tline tline tline ns tp tp
tline tdfvr tdfvf tdvsc tdvh tdhso tdef tdes NOTE
1) FREX must stay high long enough to ensure the entire sensor has been reset. 2) Shutter must be closed no later then 6000 tp after VSYNC falling edge.
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ision
Register Set
Register Set
Table 11 provides a list and description of the Device Control registers contained in the OV5620. The device slave addresses for the OV5620 are 60 for write and 61 for read.
Table 11
Address (Hex)
Device Control Register List (Sheet 1 of 9)
Register Name Default (Hex) R/W AGC Gain Control Reserved - must be set to "0" Gain setting * Range: 1x to 16x Gain = (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16) Note: Set COM8[2] = 0 to disable AGC. Digital AWB Blue Gain Control * Range: 0 to 4x ([00] to [FF]) Digital AWB Red Gain Control * Range: 0 to 4x ([00] to [FF]) Common Control 1 Dummy frame control 00: Not used 01: Allow 1 dummy frame 10: Allow 3 dummy frames 11: Allow 7 dummy frames Bit[5:4]: Reserved Bit[3:2]: Vertical window end line control 2 LSBs Bit[1:0]: Vertical window start line control 2 LSBs Register 04 Bit[7:6]: Bit[7]: Bit[6:0]: Description
00
GAIN
00
RW
01
BLUE
80
RW
02
RED
80
RW
03
COM1
4A
RW
04
REG04
00
RW
Bit[7]: Horizontal mirror Bit[6]: Vertical flip Bit[5:3]: Reserved Bit[2:0]: AEC lower 3 bits - AEC[2:0] Reserved Common Control 2 Bit[7:5]: Reserved Bit[4]: Sleep mode enable 0: Normal mode 1: Sleep mode Bit[3]: Reserved Bit[2]: Pins PWDN and RESET_B used as SLVS and SLHS, respectively Bit[1:0]: Output drive current select 00: Weakest 01: Double capability 10: Double capability 11: Triple drive current Product ID Number MSB (Read only) Product ID Number LSB (Read only) Proprietary to OmniVision Technologies, Inc. 15
05-08
RSVD
XX
-
09
COM2
01
RW
0A 0B
PIDH PIDL
56 20
R R
Version 1.1, May 9, 2006
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Table 11
Address (Hex)
Omni
ision
Device Control Register List (Sheet 2 of 9)
Register Name Default (Hex) R/W Common Control 3 Array horizontal output size select 0: 1280, if COM4[7] = 1; 864, if COM4[0] = 1; otherwise, 2592 1: 1280, if in 1.3 Mpixel, QFMD, or HF mode; 864, if in D1MD mode; otherwise, 2592 Bit[6]: Array vertical skip mode select 0: Skip 2, if COM4[6] = 1; skip 3, if COM4[5] = 1; skip 4, if COM4[4] = 1; skip 8, if COM4[3] = 1; otherwise, no skip or full mode 1: Skip 2, if in 1.3 Mpixel mode; skip 3, if in D1MD mode; skip 4, if in QFMD mode; skip 8, if in HF mode; otherwise, no skip or full mode Bit[5:4]: Reserved Bit[3]: Number of vertical blanking line select 0: 24 lines, if in full mode; 16, if in 1.3 Mpixel, D1MD, QFMD, or HF mode 1: Full mode: DMLN > 24: determined by DMLN DMLN < 24: 24 lines 1.3 Mpixel/D1MD/QFMD/HF: DMLN > 16: determined by DMLN DMLN < 16: 16 lines Note: DMLN is set by registers {DMLNH[7:0] (0x47), DMLNL[7:0] (0x46)} Array vertical output size select 0: Full mode: 1944 1.3 Mpixel: 960 D1MD: 600 QFMD: 480 HF: 240 1: Output size determined by registers COM32[7:0] and COM30[5:4] Output size = 2 x {COM32[7:0], COM30[5:4]} Bit[1]: Number of horizontal blanking line select 0: Full mode: 660 1.3 Mpixel: 360 D1MD: 436 QFMD: 332 HF: 280 1: Determined by register EXHC[11:0] Note: EXCH[11:0] is set by registers {REG2A[7:4] (0x2A), EXHCL[7:0] (0x2B)} Bit[0]: Array horizontal output size select 0: Full mode: 1944 1.3 Mpixel: 960 D1MD: 600 QFMD: 480 HF: 240 1: Output size is determined by COM31[7:0] and COM30[2:0] Output size = 2 x {COM31[7:0], COM30[2:0]} Bit[2]: Bit[7]: Description
0C
COM3
08
RW
16
Proprietary to OmniVision Technologies, Inc.
Version 1.1, May 9, 2006
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Omni
ision
Register Set
Table 11
Address (Hex)
Device Control Register List (Sheet 3 of 9)
Register Name Default (Hex) R/W Common Control 4 Bit[7:3]: Reserved Bit[2]: Clock output power-down pin status 0: Tri-state data output pin at power-down 1: Data output pin hold at last status before power-down Bit[1]: Data output pin status selection at power-down 0: Tri-state data VSYNC, PCLK, HREF, and CHSYNC pins upon power-down 1: VSYNC, PCLK, HREF, and CHSYNC pins hold on last state before power-down Bit[0]: Reserved Common Control 5 Bit[7:0]: Reserved Description
0D
COM4
06
RW
0E
COM5
01
RW
Common Control 6 Bit[7:2]: Reserved Bit[1]: Reset enable/disable when sensor working mode changes 0: Sensor timing does not reset when mode changes 1: Sensor timing resets when mode changes Bit[0]: Reserved Automatic Exposure Control - AEC[10:3] 6 MSBs (AEC[16:11]) are in register REG45[5:0] and 3 LSBs (AEC[2:0]) are in register REG04[2:0]). AEC[16:0] - Exposure time 10 AEC 63 RW TEX = tLINE x AEC[16:0] Note: The maximum exposure time is 1 frame period even if TEX is longer than 1 frame period Clock Rate Control Bit[7]: Bit[6]: 11 CLKRC 00 RW Bit[5:0]: Reserved System clock divider enable 0: Clock from PLL output 1: Enable system clock divider Clock divider If CLKRC[5:0] = 0, then CLK = PLL CLK / 2 If CLKRC[5:0] 0, then CLK = PLL CLK / [(decimal value of CLKRC[5:0] + 1) x 2]
0F
COM6
43
RW
Version 1.1, May 9, 2006
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Table 11
Address (Hex)
Omni
ision
Device Control Register List (Sheet 4 of 9)
Register Name Default (Hex) R/W Common Control 7 Bit[7]: SRST 1: Initiates soft reset. All register are set to factory default values after which the chip resumes normal operation Resolution selection 0000: 5 Mpixel (full size) mode - no binning 0001: HF mode - 1:8 binning 0010: QFMD mode - 1:4 binning 0100: D1MD mode - 1:3 binning 1000: 1.3 Mpixel mode - 1:2 binning Reserved Description
12
COM7
00
RW
Bit[6:3]:
Bit[2:0]:
Common Control 8 AEC speed selection 0: Normal 1: Faster AEC correction Bit[6:3]: Reserved Bit[2]: AGC auto/manual control selection 0: Manual 1: Auto Bit[1]: AWB auto/manual control selection 0: Manual 1: Auto Bit[0]: Exposure control 0: Manual 1: Auto Common Control 9 Bit[7:5]: AGC gain ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: Reserved 101: Reserved 110: Reserved 111: Reserved Bit[4:3]: Reserved Bit[2]: VSYNC drop option 0: VSYNC is always output 1: VSYNC is dropped if frame data is dropped Bit[1]: Frame data drop 0: Disable data drop 1: Drop frame data if exposure is not within tolerance. In AEC mode, data is normally dropped when data is out of range. Bit[0]: Reserved Bit[7]:
13
COM8
C7
RW
14
COM9
40
RW
18
Proprietary to OmniVision Technologies, Inc.
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Omni
ision
Register Set
Table 11
Address (Hex)
Device Control Register List (Sheet 5 of 9)
Register Name Default (Hex) R/W Common Control 10 Bit[7:6]: Reserved Bit[5]: PCLK output selection 0: PCLK always output 1: PCLK output qualified by HREF Bit[4]: PCLK edge selection 0: Data is updated at the failing edge of PCLK (user can latch data at the next rising edge of PCLK) 1: Data is updated at the rising edge of PCLK (user can latch data at the next falling edge of PCLK) Bit[3]: HREF output polarity 0: Output positive HREF 1: Output negative HREF, HREF negative for valid data Bit2]: Reserved Bit[1]: VSYNC polarity 0: Positive 1: Negative Bit[0]: HSYNC polarity 0: Positive 1: Negative Digital AWB Green Gain Control * Range: 0 to 4x ([00] to [FF]) Horizontal Window Start 8 MSBs (3 LSBs in REG32[2:0]) Description
15
COM10
00
RW
16
GREEN
80
RW
17
HREFST
12
RW
Bit[10:0]: Select beginning of horizontal window, each LSB represents two pixels Horizontal Window End 8 MSBs (3 LSBs in REG32[5:3]
18
HREFEND
B4 in 1.3 Mp
RW
Bit[10:0]: Select end of horizontal window, each LSB represents two pixels Vertical Window Line Start 8 MSBs (2 LSBs in register COM1[1:0])
19
VSTRT
01 in 1.3 Mp
RW
Bit[9:0]:
Selects the start of the vertical window, each LSB represents two scan lines.
1A
VEND
F4 in 1.3 Mp
Vertical Window Line End 8 MSBs (2 LSBs in register COM1[3:2]) RW Bit[9:0]: Pixel Shift Bit[7:0]: Selects the end of the vertical window, each LSB represents two scan lines.
1B
PSHFT
00
RW
Pixel delay count - provides a method to fine tune the output timing of the pixel data relative to the HREF pulse. It physically shifts the video data output time in units of pixel clock counts. The largest delay count is [FF] and is equal to 255 x PCLK. (Read only = 0x7F) (Read only = 0xA2)
1C 1D 1E-23
MIDH MIDL RSVD
7F A2 XX
R R -
Manufacturer ID Byte - High Manufacturer ID Byte - Low Reserved
Version 1.1, May 9, 2006
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Table 11
Address (Hex)
Omni
ision
Device Control Register List (Sheet 6 of 9)
Register Name Default (Hex) R/W Description Luminance Signal High Range for AEC/AGC operation AEC/AGC value decreases in auto mode when average luminance is greater than AEW[7:0] Luminance Signal Low Range for AEC/AGC operation AEC/AGC value increases in auto mode when average luminance is less than AEB[7:0] Fast Mode Large Step Range Thresholds - effective only in AEC/AGC fast mode
24
AEW
78
RW
25
AEB
68
RW
26
VV
D4
RW
Bit[7:4]: High threshold Bit[3:0]: Low threshold AEC/AGC may change in larger steps when luminance average is greater than VV[7:4] or less than VV[3:0] Reserved Register 2A
27-29
RSVD
XX
-
2A
REG2A
00
RW
Bit[7:4]: 4 MSBs of EXHC (8 LSBs in register EXHCL[7:0]) Bit[3:2]: HSYNC timing end point adjustment 2 MSBs Bit[1:0]: HSYNC timing start point adjustment 2 MSBs 8 LSBs of EXHC - pixel count in horizontal blank (valid only when COM3[1] = 1) Reserved VSYNC Pulse Width 8 LSBs
2B 2C
EXHCL RSVD
00 XX
RW -
2D
ADDVSL
00
RW
Bit[7:0]:
Line periods added to VSYNC width. Default VSYNC output width is 4 x tline. Each LSB count will add 1 x tline to the VSYNC active period.
VSYNC Pulse Width 8 MSBs 2E ADDVSH 00 RW Bit[7:0]: Line periods added to VSYNC width. Default VSYNC output width is 4 x tline. Each MSB count will add 256 x tline to the VSYNC active period.
2F
YAVG
00
RW
Luminance Average - this register will auto update HSYNC Position and Width Start 8 LSBs This register and register REG2A[1:0] define the HSYNC start position. Each LSB will shift HSYNC starting point by a 2 pixel period. HSYNC Position and Width End 8 LSBs This register and register REG2A[3:2] define the HSYNC end position. Each LSB will shift HSYNC end point by a 2 pixel period. Register 32 Bit[7:6]: Pixel clock divide option 00: No effect on PCLK 01: No effect on PCLK 10: PCLK frequency divide by 2 11: PCLK frequency divide by 4 Horizontal window end position 3 LSBs Horizontal window start position 3 LSBs
30
HSDY
08
RW
31
HEDY
30
RW
32
REG32
00 in 1.3 Mp
RW
Bit[5:3]: Bit[2:0]:
20
Proprietary to OmniVision Technologies, Inc.
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Omni
ision
Register Set
Table 11
Address (Hex) 33-44
Device Control Register List (Sheet 7 of 9)
Register Name RSVD Default (Hex) XX R/W - Reserved Register 45 Description
45
REG45
00
RW
Bit[7:6]: Bit[5:0]:
AGC[9:8], AGC 2 MSBs AEC[15:10], AEC 6 MSBs
46 47
DMLNL DMLNH
00 00
RW RW
Number of Vertical Blanking Lines LSBs Number of Vertical Blanking Lines MSBs Common Control 19
48
ZOOMSL
00
RW
Bit[7:2]: Reserved Bit[1:0]: Zoom mode vertical start window 2 LSBs (see register ZOOMSH[7:0] (0x49) for 8 MSBs) Zoom Mode Vertical Window Start Point 8 MSBs Reserved Common Control 30 Bit[7:6]: Reserved Bit[5:4]: Array vertical output size (valid only when COM3[2] = 1) Bit[3]: Reserved Bit[2:0]: Array hoizontal output size (valid only when COM3[0] = 1) Common Control 31
49 4A-5E
ZOOMSH RSVD
00 XX
RW -
5F
COM30
00
RW
60
COM31
00
RW
Bit[7:0]:
Array horizontal output size (valid only when COM3[0] = 1)
61 62
COM32 RSVD
00 XX
RW -
Common Control 32 Bit[7:0]: Reserved Common Control 34 Bit[7]: Bit[6]: Reserved De-noise enable 0: Disable 1: Enable Strength of de-noise select 0: DNSTH x 1 1: DNSTH x 4 De-noise threshold setting Array vertical output size (valid only when COM3[2] = 1)
63
COM34
00
RW Bit[5]:
Bit[4:0]: 64-7F RSVD XX - Reserved
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Table 11
Address (Hex)
Omni
ision
Device Control Register List (Sheet 8 of 9)
Register Name Default (Hex) R/W Description DSP Function Enable Control Bit[7:5]: Reserved Bit[4]: Color bar enable 0: Disable 1: Enable Bit[3:2]: Reserved Bit[1]: Raw data output select 0: Raw data after CIP 1: Raw data before CIP Bit[0]: New CIP enable 0: Disable 1: Enable DSP01 Bit[7:4]: .Bit[3]: Reserved WBC delay option when DSP01[1] and DSP01[2] are disabled 0: Do not delay 1: Delay output Black pixel canceling enable 0: Disable 1: Enable White pixel canceling enable 0: Disable 1: Enable White and black pixel canceling enable 0: Disable 1: Enable
80
DSPEN
01
RW
Bit[2]: 81 DSP01 00 RW Bit[1]:
Bit[0]:
82
RSVD
XX
-
Reserved Digital Gain Control Bit[7:2]: Bit[1:0]: Reserved Digital gain select 00: 1x 01: 2x 10: 4x 11: 4x
83
DGCTRL
80
RW
84 85 86-88
AWBBIAS DSPCTRL RSVD
00 00 XX
RW RW -
AWB Gain Bias Setting DSP Control Bit[7:0]: Reserved DSP09 Bit[7:6]: Bit[5]: Reserved AWB gain enable 0: Disable 1: Enable Reserved Version 1.1, May 9, 2006 Reserved
89
DSP09
29
RW
Bit[4:0]: 22 Proprietary to OmniVision Technologies, Inc.
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Omni
ision
Register Set
Table 11
Address (Hex) 8A
Device Control Register List (Sheet 9 of 9)
Register Name RSVD Default (Hex) XX R/W - Reserved DSP0B Bit[7:6]: Reserved Bit[5]: Gamma enable 0: Disable 1: Enable Bit[4:0]: Reserved Reserved Pixel Value Lower Limit Pixel Value Upper Limit Reserved Red Gain Limit Bit[7:4]: Description
8B
DSP0B
1F
RW
8C-A7 A8 A9 AA-B7
RSVD BOTLMT TOPLMT RSVD
XX 10 F0 XX
- RW RW -
B8
REDLMT
F0
RW Bit[3:0]:
Red gain upper limit Value = bit[7:4] x 16 + 15 Red gain lower limit Value = bit[3:0] x 16
Green Gain Limit Bit[7:4]: B9 GREENLMT F0 RW Bit[3:0]: Green gain upper limit Value = bit[7:4] x 16 + 15 Green gain lower limit Value = bit[3:0] x 16
Blue Gain Limit Bit[7:4]: BA BLUELMT F0 RW Bit[3:0]: Blue gain upper limit Value = bit[7:4] x 16 + 15 Blue gain lower limit Value = bit[3:0] x 16
BB-F6
RSVD
XX
-
Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM Package Specifications
Omni
ision
The OV5620 uses a 48-pin ceramic package. Refer to Figure 18 for package information and Figure 19 for the array center on the chip.
Figure 18 OV5620 Package Specifications
.560 SQ + .012 / - .005 .464 SQ - .005 .418 SQ - .005 42 42 43 43 .018 MIN 48 1 48 1 Pin 1 Index 66 7 7 18 18 19 19 .535 - .004 Glass Image Plane .012 TYP REF R .0075 (4 CORNERS) NOTES: 1. ALL EXPOSED METALLIZED AREAS SHALL BE GOLD-PLATED 0.50 m MIN. THK. OVER NICKEL PLATE UNLESS OTHERWISE SPECIFIED IN PURCHASE ORDER. 2. SEAL AREA AND DIE ATTACH AREA SHALL BE WITHOUT METALLIZATION.
5620CLCC_DS_018
31 31 30 30
.088 - .009 .065 - .007 .030 - .002 .015 - .002 .020 - .002
.440 - .005 .040 - .003 31 30 .022 - .002 .001 to .005 TYP .002 - .001 TYP .029 - .001 Die .038 - .007 42
.06 +.010 -.005 .040 TYP 43
Pin 1 Index
48 1
19
.020 TYP 18 R .0075 (48 PLCS) 7
6
.085 TYP
Table 12
OV5620 Package Dimensions
Dimensions Millimeters (mm) 14.22 +0.30 / -0.13 SQ 2.23 + 0.28 0.51 + 0.05 10.62 + 0.13 SQ 1.14 + 0.14 0.51 x 2.16 0.51 x 1.02 1.02 + 0.18 1.52 +0.26 / -0.13 11.18 + 0.13 13.6 + 0.1 SQ 0.55 + 0.05 0.733 + 0.015 0.95 + 0.18 1.65 + 0.18 Inches (in.) .560 +.012 / -.005 SQ .088 + .011 .020 + .002 .418 + .005 SQ .045 + .006 .020 x .085 .020 x .040 .040 + .003 .06 +.010 / -.005 .440 + .005 .535 + .004 SQ .022 + .002 .029 + .001 .037 + .007 .065 + .007 Version 1.1, May 9, 2006
Package Size Package Height Substrate Base Height Cavity Size Castellation Height Pin #1 Pad Size Pad Size Pad Pitch Package Edge to First Lead Center End-to-End Pad Center-Center Glass Size Glass Height Die Thickness Top of Glass to Image Plane Substrate Height 24 Proprietary to OmniVision Technologies, Inc.
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Omni
ision
Package Specifications
Sensor Array Center
Figure 19 OV5620 Sensor Array Center
P ac kage
Die 5808 m S ens or A rray 4294.4 m
P ac kage C enter (0, 0)
P os itional T oleranc es
1
P in 1 A rray C enter (23.2 m, -464.4 m) (0.913 mil, -18.283 mils )
Die s hift (x,y) = 0.15 mm (6 mils ) max. Die tilt = 0.75 degrees max. Die rotation = 3 degrees max.
Important:
Mos t optical s ys tems invert and mirror the image s o the chip is us ually mounted on the board with pin 1 (DOV DD) down as s hown.
5620CLCC_DS_019
NOT E : P icture is for reference only, not to s cale.
The recommended lens chief ray angle for the OV5620 is 12.5 degrees.
Version 1.1, May 9, 2006
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
IR Reflow Ramp Rate Requirements OV5620 Lead-Free Packaged Devices
Note: For OVT devices that are lead-free, all part marking letters are lower case Figure 20 IR Reflow Ramp Rate Requirements
300.0 280.0 260.0 240.0 220.0 200.0 Temperature ( C ) 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 -22 -2 0.0 18 38 0.6 58 78 1.1 98 118 1.6 138 158 2.2 178 198 2.8 218 238 3.3 258 278 3.9 298 318 Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
Omni
ision
338
358 369
Time (sec) -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
Time (min.)
5620CLCC_DS_020
Table 13
Reflow Conditions
Condition Exposure Less than 3C per second Between 330 - 600 seconds At least 210 seconds At least 30 seconds (30 ~ 120 seconds) 245C Less than 6C per second No greater than 390 seconds
Average Ramp-up Rate (30C to 217C) > 100C > 150C > 217C Peak Temperature Cool-down Rate (Peak to 50C) Time from 30C to 245C
26
Proprietary to OmniVision Technologies, Inc.
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Omni
ision
Package Specifications
Note:
* All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `VarioPixel', and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. `CameraChip' and 'OmniPixel2' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. 1341 Orleans Drive Sunnyvale, CA USA (408) 542-3000
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OV5620-CLCC Color CMOS QSXGA (5.17 MPixel) OmniPixel2TM CAMERACHIPTM
Omni
ision
28
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* Initial Release
ision
TM
REVISION CHANGE LIST
Document Title: OV5620 (CLCC) Datasheet Version: 1.0
DESCRIPTION OF CHANGES
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Omni
ision
TM
REVISION CHANGE LIST
Document Title: OV5620 (CLCC) Datasheet Version: 1.1
DESCRIPTION OF CHANGES
The following changes were made to version 1.0: * * * * * * * * * * * * * * * * Under Features on page 1, deleted (previously 11th) bulleted item "Vertical VarioPixel(R) (binning) 1:2, 1:3 Under Featuress on page 1, changed 10th bulleted item from "Horizontal VarioPixel(R) (binning) 1:2, 1:3, 1:4, 1:8" to "VarioPixel(R) (binning) 1:2, 1:3, 1:4" Under Features on page 1, changed 11th bulleted item from "Vertical skip 1:2, 1:3, 1:4, 1:8" to "Subsampling (skip) 1:2, 1:3, 1:4, 1:8" Moved section title "Horizontal VarioPixel/Binning 1:2, 1:3" to page 4 and changed it to "VarioPixel (Binning) 1:2, 1:3, 1:4" On page 4, deleted section title "Vertical VarioPixel/Binning 1:2, 1:3" On page 4, deleted "Horizontal 1:2 Skip" figure (previously Figure 8) Under General Description on page 1, changed the second line in the second paragraph from "...can also output 864 x 648 ..." to "...can also output 864 x 600 ..." Under Key Specifications on page 1, changed Digital Power Supply specification from "1.2V + 5%" to "1.3V + 5%" Under Key Specifications on page 1, changed Standby Power Requirements from "<10 A" to "250 A" Under Key Specifications on page 1, corrected Shutter specification from "Electronic rolling shutter, snapshort" to "Electronic rolling shutter, snapshot" Under Key Specifications on page 1, changed specification for Lens Chief Ray Angle from "TBD" to "12.5" Under Key Specifications on page 1, changed Max Image Transfer Rate parameter from "SXGA" to "1.3 Mpixel", from "D1" to "D1MD", and from "HF" to "QVGA" In Figure 1 on page 1, changed OV5620 chip so that pin 1 is down Under Gain Control subsection on page 3, changed the last line from "The gain adjustment range 0-42 dB" to "The gain adjustment range is 0-24 dB" On page 4, deleted section title "Vertical Skip 1:2, 1:3, 1:4, 1:8" On page 4, deleted "Vertical 1:2 Skip" figure (previously Figure 9), "Vertical 1:3 Skip" figure (previously Figure 10), "Vertical 1:4 Skip" figure (previously Figure 11), and "Vertical 1:8 Skip" figure (previously Figure 12) On page 4, added Figure 8 "Horizontal 1:4 Average (Binning)" and Figure 9 "Vertical 1:4 Average (Binning)" Under Frame Rate Adjust on page 5, changed first line from "The OV5620 offers three methods ..." to "The OV5620 offers four methods ..."
* *
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* * * * *
ision
TM
DESCRIPTION OF CHANGES (CONTINUED)
Under Frame Rate Adjust on page 5, changed the last line of the first bulleted item from "... of the input clock rate" to "... of the PLL output clock" Under Frame Rate Adjust on page 5, changed first line of the second bulleted item from "By adding a dummy pixel timing in ..." to "By changing horizontal blank timing in ..." Under Frame Rate Adjust on page 5, added "... or after the active lines (see "DMLNL" on page 21 and "DMLNH" on page 21")" to first line of third bulleted item Under Frame Rate Adjust on page 5, added a fourth bulleted item of "PLL control: Supports more flexible clock control" In the Notes for Figure 10 on page 5, changed note 2 from " Tline = 3000 x Tclk (QSXGA); Tline = 1632 x Tclk (SXGA)" to "Tline = 3252 x Tclk (QSXGA); Tline = 1640 x Tclk (1.3 Mpixel)" In the Notes for Figure 10 on page 5, changed note 3 from "Tframe = 2000 x Tline (QSXGA); Tframe = 980 x Tline (SXGA)" to "Tframe = 1968 x Tline (QSXGA); Tframe = 976 x Tline (1.3 Mpixel)" Under Power Down Mode on page 5, changed first line of the first bulleted item from "... high (+3.3VDC)..." to "... high (DOVDD)..." Under Power Down Mode on page 5, changed last line of the second bulleted item from "The current draw is less than 10 A in this standby mode" to "The current draw is less than 250 A in this standby mode" In Line/Pixel Timing section on page 6, changed the last paragraph from "The specification shown in Table 8 apply for DVDD = +1.2 V, ..." to "The specification shown in Table 8 apply for DVDD = +1.3 V, ..." In Table 2 on page 7, changed description of pin 1 from "Power for I/O circuit (1.8V to 3.3V)" to "Power for I/O circuit (1.7V to 3.3V)" In Table 2 on page 7, deleted "(1.8V to 3.3V)" from the description of pin 28 In Table 2 on page 8, changed description of pin 33 from "... or digital power (1.2V)" to "... or digital power (1.3V)" In Table 4 on page 9, changed Min, Typ, and Max for Supply voltage (DVDD) (VDD3) from "1.14", "1.2", and "1.26" to "1.24", "1.3", and "1.37", respectively In Figure 16 on page 13, added callout for VSYNC and changed Note 4 In Table 9 on page 13, added columns for VB2, VSYNC, VB1, HB1, and HB2 In Table 9 on page 13, changed Formats "XGA" and "AFMD" to "1.3Mpixel" and "HF", respectively In Table 9 on page 13, changed Frame Rate of HF (previously AFMD) from "60" to "120" In Figure 17 on page 14, deleted "tdhv" In Table 10 on page 14, deleted rows for "tvs" and "tdhv" In Table 10 on page 14, changed Typ for tline from "3000 (QSXGA)" to "3252 (QSXGA)" In Table 10 on page 14, deleted Max for tdfvf and added Typ spec of "8"
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DESCRIPTION OF CHANGES (CONTINUED)
In Table 10 on page 14, changed Typ for tdvh from "18268 (QSXGA)" to "17 (QSXGA)" and changed Unit from "tp" to "tline" In Table 10 on page 14, changed Max for tdes from "2500 (QSXGA)" to "230 (QSXGA)" In Table 11 on page 15. changed description of register GAIN (0x00) from:
AGC Gain Control Bit[7:0]: Gain setting * Range: 1x to 32x Gain = (Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16) Note: Set COM8[2] = 0 to disable AGC.
to:
AGC Gain Control Bit[7]: Reserved - must be set to "0" Bit[6:0]: Gain setting * Range: 1x to 16x Gain = (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16) Note: Set COM8[2] = 0 to disable AGC.
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In Table 11 on page 15, changed description of register BLUE (0x01) from "Range: 0 to 4x ([00] to [44])" to "Range: 0 to 4x ([00] to [FF])" In Table 11 on page 15, changed description of register RED (0x02) from "Range: 0 to 4x ([00] to [44])" to "Range: 0 to 4x ([00] to [FF])" In Table 11 on page 16, changed description for register bit COM3[7] from:
Bit[7]: Array horizontal output size select (excluding crop mode) Array horizontal output size select Array vertical skip mode select (excluding crop mode) 0: Skip 2 (output size = 960), if COM4[6] = 1; skip 3 (output size = 600), if COM4[5] = 1; skip 4 (output size = 480), if COM4[4] = 1; skip 8 (output size = 240), if COM4[3] = 1; otherwise, no skip or full mode (output size = 1944) 1: Skip 2 (output size = 960), if in XGA mode; skip 3 (output size = 600), if in D1MD mode; skip 4 (output size = 480), if in QFMD mode; skip 8 (output size = 240), if in AFMD mode; otherwise, no skip or full mode (output size = 1944) Array vertical skip mode select 0: Skip 2, if COM4[6] = 1; skip 3, if COM4[5] = 1; skip 4, if COM4[4] = 1; skip 8, if COM4[3] = 1; otherwise, no skip or full mode 1: Skip 2, if in 1.3 Mpixel mode; skip 3, if in D1MD mode; skip 4, if in QFMD mode; skip 8, if in HF mode; otherwise, no skip or full mode
to:
Bit[7]:
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In Table 11 on page 16, changed description for register bit COM3[6] from:
Bit[6]:
to:
Bit[6]:
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Bit[3]:
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DESCRIPTION OF CHANGES (CONTINUED)
In Table 11 on page 16, changed description for register bit COM3[3] from:
Number of vertical blanking line select (excluding crop mode) 0: 24 lines, if in full mode; 16, if in XGA, D1MD, QFMD, or AFMD mode 1: 24 lines, if in full mode; less than 24lines, if register DMLN is less than 24; otherwise, number of blanking lines is determined by register DMLN 16 lines, if in XGA, D1MD, QFMD, or AFMD mode; less than 16 lines, if register DMLN is less than 16; otherwise, number of blanking lines is determined by DMLN Number of vertical blanking line select 0: 24 lines, if in full mode; 16, if in 1.3 Mpixel, D1MD, QFMD, or HF mode 1: Full mode: DMLN > 24: determined by DMLN DMLN < 24: 24 lines 1.3Mpixel/D1MD/QFMD/HF: DMLN > 16: determined by DMLN 16 lines DMLN < 16: Array vertical output size select (excluding crop mode) 0: 1944, if in full mode; 960, if in XGA mode; 600, if in D1MD mode; 480, if in QFMD mode; 240, if in AFMD mode 1: Output size determined by registers COM32[7:0] and COM30[5:4] Output size = 2 x {COM32[7:0], COM30[5:4]} Array vertical output size select 0: Full mode: 1944 1.3 Mpixel: 960 D1MD: 600 QFMD: 480 HF: 240 1: Output size determined by registers COM32[7:0] and COM30[5:4] Output size = 2 x {COM32[7:0], COM30[5:4]} Number of horizontal blanking line select (excluding crop mode) 0: 660, if in full mode; 360, if in XGA mode; 436, if in D1MD mode; 280, if in AFMD mode 1: Determined by register EXHC[11:0] Number of horizontal blanking line select 0: Full mode: 660 1.3 Mpixel: 360 D1MD: 436 QFMD: 332 HF: 280 1: Determined by register EXHC[11:0]
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Bit[3]:
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In Table 11 on page 16, changed description for register bit COM3[2] from:
Bit[2]:
to:
Bit[2]:
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In Table 11 on page 16, changed description for register bit COM3[1] from:
Bit[1]:
to:
Bit[1]:
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Bit[0]:
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DESCRIPTION OF CHANGES (CONTINUED)
In Table 11 on page 16, changed description for register bit COM3[0] from:
Array horizontal output size select (excluding crop mode) 0: 1944, if in full mode; 960, if in XGA mode; 600, if in D1MD mode; 480, if in QFMD mode; 240, if in AFMD mode 1: Output size is determined by COM31[7:0] and COM30[2:0] Output size = 2 x {COM31[7:0], COM30[2:0]} Array horizontal output size select 0: Full mode: 1944 1.3 Mpixel: 960 D1MD: 600 QFMD: 480 HF: 240 1: Output size is determined by COM31[7:0] and COM30[2:0] Output size = 2 x {COM31[7:0], COM30[2:0]}
to:
Bit[0]:
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In Table 11 on page 18, changed description of register bits COM9[7:5] (0x14) from:
Bit[7:5]: AGC gain ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: Reserved 110: Reserved 111: Reserved
to:
Bit[7:5]: AGC gain ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: Reserved 101: Reserved 110: Reserved 111: Reserved
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In Table 11 on page 20, added "- pixel count in horizontal blank valid only when Reg0C[1] = 1" to description of register EXHCL (0x2B) In Table 11 on page 20, changed description for register ADDVSL[7:0] from:
VSYNC Pulse Width 8 LSBs Bit[7:0]: Line periods added to VSYNC width. Default VSYNC output width is 2 x tline. Each LSB count will add 1 x tline to the VSYNC active period.
to:
VSYNC Pulse Width 8 LSBs Bit[7:0]: Line periods added to VSYNC width. Default VSYNC output width is 4 x tline. Each LSB count will add 1 x tline to the VSYNC active period.
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In Table 11 on page 21, deleted row for register ZOOMW (0x34) In Table 11 on page 21, changed addresses for RSVD from "35-44" to "34-44" In Table 11 on page 22, changed description of register bit DSPEN[7] (0x80) to "Reserved" In Table 11 on page 23, changed address for RSVD row from "BB-DF" to "BB-F6" In Table 11 on page 23, deleted rows for registers E0 to F6 In Figure 19 on page 25, changed orientation of OV5620 chip so pin 1 is down
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